clang 20.0.0git
ARM.cpp
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1//===--- ARM.cpp - ARM (not AArch64) Helpers for Tools ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "ARM.h"
10#include "clang/Driver/Driver.h"
13#include "llvm/ADT/StringSwitch.h"
14#include "llvm/Option/ArgList.h"
15#include "llvm/TargetParser/ARMTargetParser.h"
16#include "llvm/TargetParser/Host.h"
17
18using namespace clang::driver;
19using namespace clang::driver::tools;
20using namespace clang;
21using namespace llvm::opt;
22
23// Get SubArch (vN).
24int arm::getARMSubArchVersionNumber(const llvm::Triple &Triple) {
25 llvm::StringRef Arch = Triple.getArchName();
26 return llvm::ARM::parseArchVersion(Arch);
27}
28
29// True if M-profile.
30bool arm::isARMMProfile(const llvm::Triple &Triple) {
31 llvm::StringRef Arch = Triple.getArchName();
32 return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::M;
33}
34
35// On Arm the endianness of the output file is determined by the target and
36// can be overridden by the pseudo-target flags '-mlittle-endian'/'-EL' and
37// '-mbig-endian'/'-EB'. Unlike other targets the flag does not result in a
38// normalized triple so we must handle the flag here.
39bool arm::isARMBigEndian(const llvm::Triple &Triple, const ArgList &Args) {
40 if (Arg *A = Args.getLastArg(options::OPT_mlittle_endian,
41 options::OPT_mbig_endian)) {
42 return !A->getOption().matches(options::OPT_mlittle_endian);
43 }
44
45 return Triple.getArch() == llvm::Triple::armeb ||
46 Triple.getArch() == llvm::Triple::thumbeb;
47}
48
49// True if A-profile.
50bool arm::isARMAProfile(const llvm::Triple &Triple) {
51 llvm::StringRef Arch = Triple.getArchName();
52 return llvm::ARM::parseArchProfile(Arch) == llvm::ARM::ProfileKind::A;
53}
54
55/// Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
56bool arm::isARMEABIBareMetal(const llvm::Triple &Triple) {
57 auto arch = Triple.getArch();
58 if (arch != llvm::Triple::arm && arch != llvm::Triple::thumb &&
59 arch != llvm::Triple::armeb && arch != llvm::Triple::thumbeb)
60 return false;
61
62 if (Triple.getVendor() != llvm::Triple::UnknownVendor)
63 return false;
64
65 if (Triple.getOS() != llvm::Triple::UnknownOS)
66 return false;
67
68 if (Triple.getEnvironment() != llvm::Triple::EABI &&
69 Triple.getEnvironment() != llvm::Triple::EABIHF)
70 return false;
71
72 return true;
73}
74
75// Get Arch/CPU from args.
76void arm::getARMArchCPUFromArgs(const ArgList &Args, llvm::StringRef &Arch,
77 llvm::StringRef &CPU, bool FromAs) {
78 if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ))
79 CPU = A->getValue();
80 if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
81 Arch = A->getValue();
82 if (!FromAs)
83 return;
84
85 for (const Arg *A :
86 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
87 // Use getValues because -Wa can have multiple arguments
88 // e.g. -Wa,-mcpu=foo,-mcpu=bar
89 for (StringRef Value : A->getValues()) {
90 if (Value.starts_with("-mcpu="))
91 CPU = Value.substr(6);
92 if (Value.starts_with("-march="))
93 Arch = Value.substr(7);
94 }
95 }
96}
97
98// Handle -mhwdiv=.
99// FIXME: Use ARMTargetParser.
100static void getARMHWDivFeatures(const Driver &D, const Arg *A,
101 const ArgList &Args, StringRef HWDiv,
102 std::vector<StringRef> &Features) {
103 uint64_t HWDivID = llvm::ARM::parseHWDiv(HWDiv);
104 if (!llvm::ARM::getHWDivFeatures(HWDivID, Features))
105 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
106}
107
108// Handle -mfpu=.
109static llvm::ARM::FPUKind getARMFPUFeatures(const Driver &D, const Arg *A,
110 const ArgList &Args, StringRef FPU,
111 std::vector<StringRef> &Features) {
112 llvm::ARM::FPUKind FPUKind = llvm::ARM::parseFPU(FPU);
113 if (!llvm::ARM::getFPUFeatures(FPUKind, Features))
114 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
115 return FPUKind;
116}
117
118// Decode ARM features from string like +[no]featureA+[no]featureB+...
119static bool DecodeARMFeatures(const Driver &D, StringRef text, StringRef CPU,
120 llvm::ARM::ArchKind ArchKind,
121 std::vector<StringRef> &Features,
122 llvm::ARM::FPUKind &ArgFPUKind) {
124 text.split(Split, StringRef("+"), -1, false);
125
126 for (StringRef Feature : Split) {
127 if (!appendArchExtFeatures(CPU, ArchKind, Feature, Features, ArgFPUKind))
128 return false;
129 }
130 return true;
131}
132
133static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU,
134 std::vector<StringRef> &Features) {
135 CPU = CPU.split("+").first;
136 if (CPU != "generic") {
137 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
138 uint64_t Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
139 llvm::ARM::getExtensionFeatures(Extension, Features);
140 }
141}
142
143// Check if -march is valid by checking if it can be canonicalised and parsed.
144// getARMArch is used here instead of just checking the -march value in order
145// to handle -march=native correctly.
146static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args,
147 llvm::StringRef ArchName, llvm::StringRef CPUName,
148 std::vector<StringRef> &Features,
149 const llvm::Triple &Triple,
150 llvm::ARM::FPUKind &ArgFPUKind) {
151 std::pair<StringRef, StringRef> Split = ArchName.split("+");
152
153 std::string MArch = arm::getARMArch(ArchName, Triple);
154 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseArch(MArch);
155 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
156 (Split.second.size() &&
157 !DecodeARMFeatures(D, Split.second, CPUName, ArchKind, Features,
158 ArgFPUKind)))
159 D.Diag(clang::diag::err_drv_unsupported_option_argument)
160 << A->getSpelling() << A->getValue();
161}
162
163// Check -mcpu=. Needs ArchName to handle -mcpu=generic.
164static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args,
165 llvm::StringRef CPUName, llvm::StringRef ArchName,
166 std::vector<StringRef> &Features,
167 const llvm::Triple &Triple,
168 llvm::ARM::FPUKind &ArgFPUKind) {
169 std::pair<StringRef, StringRef> Split = CPUName.split("+");
170
171 std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
172 llvm::ARM::ArchKind ArchKind =
173 arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
174 if (ArchKind == llvm::ARM::ArchKind::INVALID ||
175 (Split.second.size() && !DecodeARMFeatures(D, Split.second, CPU, ArchKind,
176 Features, ArgFPUKind)))
177 D.Diag(clang::diag::err_drv_unsupported_option_argument)
178 << A->getSpelling() << A->getValue();
179}
180
181// If -mfloat-abi=hard or -mhard-float are specified explicitly then check that
182// floating point registers are available on the target CPU.
183static void checkARMFloatABI(const Driver &D, const ArgList &Args,
184 bool HasFPRegs) {
185 if (HasFPRegs)
186 return;
187 const Arg *A =
188 Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
189 options::OPT_mfloat_abi_EQ);
190 if (A && (A->getOption().matches(options::OPT_mhard_float) ||
191 (A->getOption().matches(options::OPT_mfloat_abi_EQ) &&
192 A->getValue() == StringRef("hard"))))
193 D.Diag(clang::diag::warn_drv_no_floating_point_registers)
194 << A->getAsString(Args);
195}
196
197bool arm::useAAPCSForMachO(const llvm::Triple &T) {
198 // The backend is hardwired to assume AAPCS for M-class processors, ensure
199 // the frontend matches that.
200 return T.getEnvironment() == llvm::Triple::EABI ||
201 T.getEnvironment() == llvm::Triple::EABIHF ||
202 T.getOS() == llvm::Triple::UnknownOS || isARMMProfile(T);
203}
204
205// We follow GCC and support when the backend has support for the MRC/MCR
206// instructions that are used to set the hard thread pointer ("CP15 C13
207// Thread id").
208bool arm::isHardTPSupported(const llvm::Triple &Triple) {
209 int Ver = getARMSubArchVersionNumber(Triple);
210 llvm::ARM::ArchKind AK = llvm::ARM::parseArch(Triple.getArchName());
211 return Triple.isARM() || AK == llvm::ARM::ArchKind::ARMV6T2 ||
212 (Ver >= 7 && AK != llvm::ARM::ArchKind::ARMV8MBaseline);
213}
214
215// Select mode for reading thread pointer (-mtp=soft/cp15).
216arm::ReadTPMode arm::getReadTPMode(const Driver &D, const ArgList &Args,
217 const llvm::Triple &Triple, bool ForAS) {
218 if (Arg *A = Args.getLastArg(options::OPT_mtp_mode_EQ)) {
219 arm::ReadTPMode ThreadPointer =
220 llvm::StringSwitch<arm::ReadTPMode>(A->getValue())
221 .Case("cp15", ReadTPMode::TPIDRURO)
222 .Case("tpidrurw", ReadTPMode::TPIDRURW)
223 .Case("tpidruro", ReadTPMode::TPIDRURO)
224 .Case("tpidrprw", ReadTPMode::TPIDRPRW)
225 .Case("soft", ReadTPMode::Soft)
226 .Default(ReadTPMode::Invalid);
227 if ((ThreadPointer == ReadTPMode::TPIDRURW ||
228 ThreadPointer == ReadTPMode::TPIDRURO ||
229 ThreadPointer == ReadTPMode::TPIDRPRW) &&
230 !isHardTPSupported(Triple) && !ForAS) {
231 D.Diag(diag::err_target_unsupported_tp_hard) << Triple.getArchName();
232 return ReadTPMode::Invalid;
233 }
234 if (ThreadPointer != ReadTPMode::Invalid)
235 return ThreadPointer;
236 if (StringRef(A->getValue()).empty())
237 D.Diag(diag::err_drv_missing_arg_mtp) << A->getAsString(Args);
238 else
239 D.Diag(diag::err_drv_invalid_mtp) << A->getAsString(Args);
240 return ReadTPMode::Invalid;
241 }
242 return ReadTPMode::Soft;
243}
244
245void arm::setArchNameInTriple(const Driver &D, const ArgList &Args,
246 types::ID InputType, llvm::Triple &Triple) {
247 StringRef MCPU, MArch;
248 if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
249 MCPU = A->getValue();
250 if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
251 MArch = A->getValue();
252
253 std::string CPU = Triple.isOSBinFormatMachO()
254 ? tools::arm::getARMCPUForMArch(MArch, Triple).str()
255 : tools::arm::getARMTargetCPU(MCPU, MArch, Triple);
256 StringRef Suffix = tools::arm::getLLVMArchSuffixForARM(CPU, MArch, Triple);
257
258 bool IsBigEndian = Triple.getArch() == llvm::Triple::armeb ||
259 Triple.getArch() == llvm::Triple::thumbeb;
260 // Handle pseudo-target flags '-mlittle-endian'/'-EL' and
261 // '-mbig-endian'/'-EB'.
262 if (Arg *A = Args.getLastArg(options::OPT_mlittle_endian,
263 options::OPT_mbig_endian)) {
264 IsBigEndian = !A->getOption().matches(options::OPT_mlittle_endian);
265 }
266 std::string ArchName = IsBigEndian ? "armeb" : "arm";
267
268 // FIXME: Thumb should just be another -target-feaure, not in the triple.
269 bool IsMProfile =
270 llvm::ARM::parseArchProfile(Suffix) == llvm::ARM::ProfileKind::M;
271 bool ThumbDefault = IsMProfile ||
272 // Thumb2 is the default for V7 on Darwin.
273 (llvm::ARM::parseArchVersion(Suffix) == 7 &&
274 Triple.isOSBinFormatMachO()) ||
275 // FIXME: this is invalid for WindowsCE
276 Triple.isOSWindows();
277
278 // Check if ARM ISA was explicitly selected (using -mno-thumb or -marm) for
279 // M-Class CPUs/architecture variants, which is not supported.
280 bool ARMModeRequested =
281 !Args.hasFlag(options::OPT_mthumb, options::OPT_mno_thumb, ThumbDefault);
282 if (IsMProfile && ARMModeRequested) {
283 if (MCPU.size())
284 D.Diag(diag::err_cpu_unsupported_isa) << CPU << "ARM";
285 else
286 D.Diag(diag::err_arch_unsupported_isa)
287 << tools::arm::getARMArch(MArch, Triple) << "ARM";
288 }
289
290 // Check to see if an explicit choice to use thumb has been made via
291 // -mthumb. For assembler files we must check for -mthumb in the options
292 // passed to the assembler via -Wa or -Xassembler.
293 bool IsThumb = false;
294 if (InputType != types::TY_PP_Asm)
295 IsThumb =
296 Args.hasFlag(options::OPT_mthumb, options::OPT_mno_thumb, ThumbDefault);
297 else {
298 // Ideally we would check for these flags in
299 // CollectArgsForIntegratedAssembler but we can't change the ArchName at
300 // that point.
301 llvm::StringRef WaMArch, WaMCPU;
302 for (const auto *A :
303 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
304 for (StringRef Value : A->getValues()) {
305 // There is no assembler equivalent of -mno-thumb, -marm, or -mno-arm.
306 if (Value == "-mthumb")
307 IsThumb = true;
308 else if (Value.starts_with("-march="))
309 WaMArch = Value.substr(7);
310 else if (Value.starts_with("-mcpu="))
311 WaMCPU = Value.substr(6);
312 }
313 }
314
315 if (WaMCPU.size() || WaMArch.size()) {
316 // The way this works means that we prefer -Wa,-mcpu's architecture
317 // over -Wa,-march. Which matches the compiler behaviour.
318 Suffix = tools::arm::getLLVMArchSuffixForARM(WaMCPU, WaMArch, Triple);
319 }
320 }
321
322 // Assembly files should start in ARM mode, unless arch is M-profile, or
323 // -mthumb has been passed explicitly to the assembler. Windows is always
324 // thumb.
325 if (IsThumb || IsMProfile || Triple.isOSWindows()) {
326 if (IsBigEndian)
327 ArchName = "thumbeb";
328 else
329 ArchName = "thumb";
330 }
331 Triple.setArchName(ArchName + Suffix.str());
332}
333
334void arm::setFloatABIInTriple(const Driver &D, const ArgList &Args,
335 llvm::Triple &Triple) {
336 if (Triple.isOSLiteOS()) {
337 Triple.setEnvironment(llvm::Triple::OpenHOS);
338 return;
339 }
340
341 bool isHardFloat =
342 (arm::getARMFloatABI(D, Triple, Args) == arm::FloatABI::Hard);
343
344 switch (Triple.getEnvironment()) {
345 case llvm::Triple::GNUEABI:
346 case llvm::Triple::GNUEABIHF:
347 Triple.setEnvironment(isHardFloat ? llvm::Triple::GNUEABIHF
348 : llvm::Triple::GNUEABI);
349 break;
350 case llvm::Triple::GNUEABIT64:
351 case llvm::Triple::GNUEABIHFT64:
352 Triple.setEnvironment(isHardFloat ? llvm::Triple::GNUEABIHFT64
353 : llvm::Triple::GNUEABIT64);
354 break;
355 case llvm::Triple::EABI:
356 case llvm::Triple::EABIHF:
357 Triple.setEnvironment(isHardFloat ? llvm::Triple::EABIHF
358 : llvm::Triple::EABI);
359 break;
360 case llvm::Triple::MuslEABI:
361 case llvm::Triple::MuslEABIHF:
362 Triple.setEnvironment(isHardFloat ? llvm::Triple::MuslEABIHF
363 : llvm::Triple::MuslEABI);
364 break;
365 case llvm::Triple::OpenHOS:
366 break;
367 default: {
368 arm::FloatABI DefaultABI = arm::getDefaultFloatABI(Triple);
369 if (DefaultABI != arm::FloatABI::Invalid &&
370 isHardFloat != (DefaultABI == arm::FloatABI::Hard)) {
371 Arg *ABIArg =
372 Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
373 options::OPT_mfloat_abi_EQ);
374 assert(ABIArg && "Non-default float abi expected to be from arg");
375 D.Diag(diag::err_drv_unsupported_opt_for_target)
376 << ABIArg->getAsString(Args) << Triple.getTriple();
377 }
378 break;
379 }
380 }
381}
382
383arm::FloatABI arm::getARMFloatABI(const ToolChain &TC, const ArgList &Args) {
384 return arm::getARMFloatABI(TC.getDriver(), TC.getEffectiveTriple(), Args);
385}
386
387arm::FloatABI arm::getDefaultFloatABI(const llvm::Triple &Triple) {
388 auto SubArch = getARMSubArchVersionNumber(Triple);
389 switch (Triple.getOS()) {
390 case llvm::Triple::Darwin:
391 case llvm::Triple::MacOSX:
392 case llvm::Triple::IOS:
393 case llvm::Triple::TvOS:
394 case llvm::Triple::DriverKit:
395 case llvm::Triple::XROS:
396 // Darwin defaults to "softfp" for v6 and v7.
397 if (Triple.isWatchABI())
398 return FloatABI::Hard;
399 else
400 return (SubArch == 6 || SubArch == 7) ? FloatABI::SoftFP : FloatABI::Soft;
401
402 case llvm::Triple::WatchOS:
403 return FloatABI::Hard;
404
405 // FIXME: this is invalid for WindowsCE
406 case llvm::Triple::Win32:
407 // It is incorrect to select hard float ABI on MachO platforms if the ABI is
408 // "apcs-gnu".
409 if (Triple.isOSBinFormatMachO() && !useAAPCSForMachO(Triple))
410 return FloatABI::Soft;
411 return FloatABI::Hard;
412
413 case llvm::Triple::NetBSD:
414 switch (Triple.getEnvironment()) {
415 case llvm::Triple::EABIHF:
416 case llvm::Triple::GNUEABIHF:
417 return FloatABI::Hard;
418 default:
419 return FloatABI::Soft;
420 }
421 break;
422
423 case llvm::Triple::FreeBSD:
424 switch (Triple.getEnvironment()) {
425 case llvm::Triple::GNUEABIHF:
426 return FloatABI::Hard;
427 default:
428 // FreeBSD defaults to soft float
429 return FloatABI::Soft;
430 }
431 break;
432
433 case llvm::Triple::Haiku:
434 case llvm::Triple::OpenBSD:
435 return FloatABI::SoftFP;
436
437 default:
438 if (Triple.isOHOSFamily())
439 return FloatABI::Soft;
440 switch (Triple.getEnvironment()) {
441 case llvm::Triple::GNUEABIHF:
442 case llvm::Triple::GNUEABIHFT64:
443 case llvm::Triple::MuslEABIHF:
444 case llvm::Triple::EABIHF:
445 return FloatABI::Hard;
446 case llvm::Triple::GNUEABI:
447 case llvm::Triple::GNUEABIT64:
448 case llvm::Triple::MuslEABI:
449 case llvm::Triple::EABI:
450 // EABI is always AAPCS, and if it was not marked 'hard', it's softfp
451 return FloatABI::SoftFP;
452 case llvm::Triple::Android:
453 return (SubArch >= 7) ? FloatABI::SoftFP : FloatABI::Soft;
454 default:
455 return FloatABI::Invalid;
456 }
457 }
458 return FloatABI::Invalid;
459}
460
461// Select the float ABI as determined by -msoft-float, -mhard-float, and
462// -mfloat-abi=.
463arm::FloatABI arm::getARMFloatABI(const Driver &D, const llvm::Triple &Triple,
464 const ArgList &Args) {
465 arm::FloatABI ABI = FloatABI::Invalid;
466 if (Arg *A =
467 Args.getLastArg(options::OPT_msoft_float, options::OPT_mhard_float,
468 options::OPT_mfloat_abi_EQ)) {
469 if (A->getOption().matches(options::OPT_msoft_float)) {
470 ABI = FloatABI::Soft;
471 } else if (A->getOption().matches(options::OPT_mhard_float)) {
472 ABI = FloatABI::Hard;
473 } else {
474 ABI = llvm::StringSwitch<arm::FloatABI>(A->getValue())
475 .Case("soft", FloatABI::Soft)
476 .Case("softfp", FloatABI::SoftFP)
477 .Case("hard", FloatABI::Hard)
478 .Default(FloatABI::Invalid);
479 if (ABI == FloatABI::Invalid && !StringRef(A->getValue()).empty()) {
480 D.Diag(diag::err_drv_invalid_mfloat_abi) << A->getAsString(Args);
481 ABI = FloatABI::Soft;
482 }
483 }
484 }
485
486 // If unspecified, choose the default based on the platform.
487 if (ABI == FloatABI::Invalid)
488 ABI = arm::getDefaultFloatABI(Triple);
489
490 if (ABI == FloatABI::Invalid) {
491 // Assume "soft", but warn the user we are guessing.
492 if (Triple.isOSBinFormatMachO() &&
493 Triple.getSubArch() == llvm::Triple::ARMSubArch_v7em)
494 ABI = FloatABI::Hard;
495 else
496 ABI = FloatABI::Soft;
497
498 if (Triple.getOS() != llvm::Triple::UnknownOS ||
499 !Triple.isOSBinFormatMachO())
500 D.Diag(diag::warn_drv_assuming_mfloat_abi_is) << "soft";
501 }
502
503 assert(ABI != FloatABI::Invalid && "must select an ABI");
504 return ABI;
505}
506
507static bool hasIntegerMVE(const std::vector<StringRef> &F) {
508 auto MVE = llvm::find(llvm::reverse(F), "+mve");
509 auto NoMVE = llvm::find(llvm::reverse(F), "-mve");
510 return MVE != F.rend() &&
511 (NoMVE == F.rend() || std::distance(MVE, NoMVE) > 0);
512}
513
514llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
515 const llvm::Triple &Triple,
516 const ArgList &Args,
517 std::vector<StringRef> &Features,
518 bool ForAS, bool ForMultilib) {
519 bool KernelOrKext =
520 Args.hasArg(options::OPT_mkernel, options::OPT_fapple_kext);
521 arm::FloatABI ABI = arm::getARMFloatABI(D, Triple, Args);
522 std::optional<std::pair<const Arg *, StringRef>> WaCPU, WaFPU, WaHDiv, WaArch;
523
524 // This vector will accumulate features from the architecture
525 // extension suffixes on -mcpu and -march (e.g. the 'bar' in
526 // -mcpu=foo+bar). We want to apply those after the features derived
527 // from the FPU, in case -mfpu generates a negative feature which
528 // the +bar is supposed to override.
529 std::vector<StringRef> ExtensionFeatures;
530
531 if (!ForAS) {
532 // FIXME: Note, this is a hack, the LLVM backend doesn't actually use these
533 // yet (it uses the -mfloat-abi and -msoft-float options), and it is
534 // stripped out by the ARM target. We should probably pass this a new
535 // -target-option, which is handled by the -cc1/-cc1as invocation.
536 //
537 // FIXME2: For consistency, it would be ideal if we set up the target
538 // machine state the same when using the frontend or the assembler. We don't
539 // currently do that for the assembler, we pass the options directly to the
540 // backend and never even instantiate the frontend TargetInfo. If we did,
541 // and used its handleTargetFeatures hook, then we could ensure the
542 // assembler and the frontend behave the same.
543
544 // Use software floating point operations?
545 if (ABI == arm::FloatABI::Soft)
546 Features.push_back("+soft-float");
547
548 // Use software floating point argument passing?
549 if (ABI != arm::FloatABI::Hard)
550 Features.push_back("+soft-float-abi");
551 } else {
552 // Here, we make sure that -Wa,-mfpu/cpu/arch/hwdiv will be passed down
553 // to the assembler correctly.
554 for (const Arg *A :
555 Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) {
556 // We use getValues here because you can have many options per -Wa
557 // We will keep the last one we find for each of these
558 for (StringRef Value : A->getValues()) {
559 if (Value.starts_with("-mfpu=")) {
560 WaFPU = std::make_pair(A, Value.substr(6));
561 } else if (Value.starts_with("-mcpu=")) {
562 WaCPU = std::make_pair(A, Value.substr(6));
563 } else if (Value.starts_with("-mhwdiv=")) {
564 WaHDiv = std::make_pair(A, Value.substr(8));
565 } else if (Value.starts_with("-march=")) {
566 WaArch = std::make_pair(A, Value.substr(7));
567 }
568 }
569 }
570
571 // The integrated assembler doesn't implement e_flags setting behavior for
572 // -meabi=gnu (gcc -mabi={apcs-gnu,atpcs} passes -meabi=gnu to gas). For
573 // compatibility we accept but warn.
574 if (Arg *A = Args.getLastArgNoClaim(options::OPT_mabi_EQ))
575 A->ignoreTargetSpecific();
576 }
577
578 if (getReadTPMode(D, Args, Triple, ForAS) == ReadTPMode::TPIDRURW)
579 Features.push_back("+read-tp-tpidrurw");
580 if (getReadTPMode(D, Args, Triple, ForAS) == ReadTPMode::TPIDRURO)
581 Features.push_back("+read-tp-tpidruro");
582 if (getReadTPMode(D, Args, Triple, ForAS) == ReadTPMode::TPIDRPRW)
583 Features.push_back("+read-tp-tpidrprw");
584
585 const Arg *ArchArg = Args.getLastArg(options::OPT_march_EQ);
586 const Arg *CPUArg = Args.getLastArg(options::OPT_mcpu_EQ);
587 StringRef ArchName;
588 StringRef CPUName;
589 llvm::ARM::FPUKind ArchArgFPUKind = llvm::ARM::FK_INVALID;
590 llvm::ARM::FPUKind CPUArgFPUKind = llvm::ARM::FK_INVALID;
591
592 // Check -mcpu. ClangAs gives preference to -Wa,-mcpu=.
593 if (WaCPU) {
594 if (CPUArg)
595 D.Diag(clang::diag::warn_drv_unused_argument)
596 << CPUArg->getAsString(Args);
597 CPUName = WaCPU->second;
598 CPUArg = WaCPU->first;
599 } else if (CPUArg)
600 CPUName = CPUArg->getValue();
601
602 // Check -march. ClangAs gives preference to -Wa,-march=.
603 if (WaArch) {
604 if (ArchArg)
605 D.Diag(clang::diag::warn_drv_unused_argument)
606 << ArchArg->getAsString(Args);
607 ArchName = WaArch->second;
608 // This will set any features after the base architecture.
609 checkARMArchName(D, WaArch->first, Args, ArchName, CPUName,
610 ExtensionFeatures, Triple, ArchArgFPUKind);
611 // The base architecture was handled in ToolChain::ComputeLLVMTriple because
612 // triple is read only by this point.
613 } else if (ArchArg) {
614 ArchName = ArchArg->getValue();
615 checkARMArchName(D, ArchArg, Args, ArchName, CPUName, ExtensionFeatures,
616 Triple, ArchArgFPUKind);
617 }
618
619 // Add CPU features for generic CPUs
620 if (CPUName == "native") {
621 for (auto &F : llvm::sys::getHostCPUFeatures())
622 Features.push_back(
623 Args.MakeArgString((F.second ? "+" : "-") + F.first()));
624 } else if (!CPUName.empty()) {
625 // This sets the default features for the specified CPU. We certainly don't
626 // want to override the features that have been explicitly specified on the
627 // command line. Therefore, process them directly instead of appending them
628 // at the end later.
629 DecodeARMFeaturesFromCPU(D, CPUName, Features);
630 }
631
632 if (CPUArg)
633 checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, ExtensionFeatures,
634 Triple, CPUArgFPUKind);
635
636 // TODO Handle -mtune=. Suppress -Wunused-command-line-argument as a
637 // longstanding behavior.
638 (void)Args.getLastArg(options::OPT_mtune_EQ);
639
640 // Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.
641 llvm::ARM::FPUKind FPUKind = llvm::ARM::FK_INVALID;
642 const Arg *FPUArg = Args.getLastArg(options::OPT_mfpu_EQ);
643 if (WaFPU) {
644 if (FPUArg)
645 D.Diag(clang::diag::warn_drv_unused_argument)
646 << FPUArg->getAsString(Args);
647 (void)getARMFPUFeatures(D, WaFPU->first, Args, WaFPU->second, Features);
648 } else if (FPUArg) {
649 FPUKind = getARMFPUFeatures(D, FPUArg, Args, FPUArg->getValue(), Features);
650 } else if (Triple.isAndroid() && getARMSubArchVersionNumber(Triple) == 7) {
651 const char *AndroidFPU = "neon";
652 FPUKind = llvm::ARM::parseFPU(AndroidFPU);
653 if (!llvm::ARM::getFPUFeatures(FPUKind, Features))
654 D.Diag(clang::diag::err_drv_clang_unsupported)
655 << std::string("-mfpu=") + AndroidFPU;
656 } else if (ArchArgFPUKind != llvm::ARM::FK_INVALID ||
657 CPUArgFPUKind != llvm::ARM::FK_INVALID) {
658 FPUKind =
659 CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind : ArchArgFPUKind;
660 (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
661 } else {
662 bool Generic = true;
663 if (!ForAS) {
664 std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
665 if (CPU != "generic")
666 Generic = false;
667 llvm::ARM::ArchKind ArchKind =
668 arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
669 FPUKind = llvm::ARM::getDefaultFPU(CPU, ArchKind);
670 (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
671 }
672 if (Generic && (Triple.isOSWindows() || Triple.isOSDarwin()) &&
673 getARMSubArchVersionNumber(Triple) >= 7) {
674 FPUKind = llvm::ARM::parseFPU("neon");
675 (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
676 }
677 }
678
679 // Now we've finished accumulating features from arch, cpu and fpu,
680 // we can append the ones for architecture extensions that we
681 // collected separately.
682 Features.insert(std::end(Features),
683 std::begin(ExtensionFeatures), std::end(ExtensionFeatures));
684
685 // Honor -mhwdiv=. ClangAs gives preference to -Wa,-mhwdiv=.
686 const Arg *HDivArg = Args.getLastArg(options::OPT_mhwdiv_EQ);
687 if (WaHDiv) {
688 if (HDivArg)
689 D.Diag(clang::diag::warn_drv_unused_argument)
690 << HDivArg->getAsString(Args);
691 getARMHWDivFeatures(D, WaHDiv->first, Args, WaHDiv->second, Features);
692 } else if (HDivArg)
693 getARMHWDivFeatures(D, HDivArg, Args, HDivArg->getValue(), Features);
694
695 // Handle (arch-dependent) fp16fml/fullfp16 relationship.
696 // Must happen before any features are disabled due to soft-float.
697 // FIXME: this fp16fml option handling will be reimplemented after the
698 // TargetParser rewrite.
699 const auto ItRNoFullFP16 = std::find(Features.rbegin(), Features.rend(), "-fullfp16");
700 const auto ItRFP16FML = std::find(Features.rbegin(), Features.rend(), "+fp16fml");
701 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8_4a) {
702 const auto ItRFullFP16 = std::find(Features.rbegin(), Features.rend(), "+fullfp16");
703 if (ItRFullFP16 < ItRNoFullFP16 && ItRFullFP16 < ItRFP16FML) {
704 // Only entangled feature that can be to the right of this +fullfp16 is -fp16fml.
705 // Only append the +fp16fml if there is no -fp16fml after the +fullfp16.
706 if (std::find(Features.rbegin(), ItRFullFP16, "-fp16fml") == ItRFullFP16)
707 Features.push_back("+fp16fml");
708 }
709 else
710 goto fp16_fml_fallthrough;
711 }
712 else {
713fp16_fml_fallthrough:
714 // In both of these cases, putting the 'other' feature on the end of the vector will
715 // result in the same effect as placing it immediately after the current feature.
716 if (ItRNoFullFP16 < ItRFP16FML)
717 Features.push_back("-fp16fml");
718 else if (ItRNoFullFP16 > ItRFP16FML)
719 Features.push_back("+fullfp16");
720 }
721
722 // Setting -msoft-float/-mfloat-abi=soft, -mfpu=none, or adding +nofp to
723 // -march/-mcpu effectively disables the FPU (GCC ignores the -mfpu options in
724 // this case). Note that the ABI can also be set implicitly by the target
725 // selected.
726 bool HasFPRegs = true;
727 if (ABI == arm::FloatABI::Soft) {
728 llvm::ARM::getFPUFeatures(llvm::ARM::FK_NONE, Features);
729
730 // Disable all features relating to hardware FP, not already disabled by the
731 // above call.
732 Features.insert(Features.end(),
733 {"-dotprod", "-fp16fml", "-bf16", "-mve", "-mve.fp"});
734 HasFPRegs = false;
735 FPUKind = llvm::ARM::FK_NONE;
736 } else if (FPUKind == llvm::ARM::FK_NONE ||
737 ArchArgFPUKind == llvm::ARM::FK_NONE ||
738 CPUArgFPUKind == llvm::ARM::FK_NONE) {
739 // -mfpu=none, -march=armvX+nofp or -mcpu=X+nofp is *very* similar to
740 // -mfloat-abi=soft, only that it should not disable MVE-I. They disable the
741 // FPU, but not the FPU registers, thus MVE-I, which depends only on the
742 // latter, is still supported.
743 Features.insert(Features.end(),
744 {"-dotprod", "-fp16fml", "-bf16", "-mve.fp"});
745 HasFPRegs = hasIntegerMVE(Features);
746 FPUKind = llvm::ARM::FK_NONE;
747 }
748 if (!HasFPRegs)
749 Features.emplace_back("-fpregs");
750
751 // En/disable crc code generation.
752 if (Arg *A = Args.getLastArg(options::OPT_mcrc, options::OPT_mnocrc)) {
753 if (A->getOption().matches(options::OPT_mcrc))
754 Features.push_back("+crc");
755 else
756 Features.push_back("-crc");
757 }
758
759 // For Arch >= ARMv8.0 && A or R profile: crypto = sha2 + aes
760 // Rather than replace within the feature vector, determine whether each
761 // algorithm is enabled and append this to the end of the vector.
762 // The algorithms can be controlled by their specific feature or the crypto
763 // feature, so their status can be determined by the last occurance of
764 // either in the vector. This allows one to supercede the other.
765 // e.g. +crypto+noaes in -march/-mcpu should enable sha2, but not aes
766 // FIXME: this needs reimplementation after the TargetParser rewrite
767 bool HasSHA2 = false;
768 bool HasAES = false;
769 const auto ItCrypto =
770 llvm::find_if(llvm::reverse(Features), [](const StringRef F) {
771 return F.contains("crypto");
772 });
773 const auto ItSHA2 =
774 llvm::find_if(llvm::reverse(Features), [](const StringRef F) {
775 return F.contains("crypto") || F.contains("sha2");
776 });
777 const auto ItAES =
778 llvm::find_if(llvm::reverse(Features), [](const StringRef F) {
779 return F.contains("crypto") || F.contains("aes");
780 });
781 const bool FoundSHA2 = ItSHA2 != Features.rend();
782 const bool FoundAES = ItAES != Features.rend();
783 if (FoundSHA2)
784 HasSHA2 = ItSHA2->take_front() == "+";
785 if (FoundAES)
786 HasAES = ItAES->take_front() == "+";
787 if (ItCrypto != Features.rend()) {
788 if (HasSHA2 && HasAES)
789 Features.push_back("+crypto");
790 else
791 Features.push_back("-crypto");
792 if (HasSHA2)
793 Features.push_back("+sha2");
794 else
795 Features.push_back("-sha2");
796 if (HasAES)
797 Features.push_back("+aes");
798 else
799 Features.push_back("-aes");
800 }
801
802 if (HasSHA2 || HasAES) {
803 StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
804 arm::getARMTargetCPU(CPUName, ArchName, Triple), ArchName, Triple);
805 llvm::ARM::ProfileKind ArchProfile =
806 llvm::ARM::parseArchProfile(ArchSuffix);
807 if (!((llvm::ARM::parseArchVersion(ArchSuffix) >= 8) &&
808 (ArchProfile == llvm::ARM::ProfileKind::A ||
809 ArchProfile == llvm::ARM::ProfileKind::R))) {
810 if (HasSHA2)
811 D.Diag(clang::diag::warn_target_unsupported_extension)
812 << "sha2"
813 << llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
814 if (HasAES)
815 D.Diag(clang::diag::warn_target_unsupported_extension)
816 << "aes"
817 << llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
818 // With -fno-integrated-as -mfpu=crypto-neon-fp-armv8 some assemblers such
819 // as the GNU assembler will permit the use of crypto instructions as the
820 // fpu will override the architecture. We keep the crypto feature in this
821 // case to preserve compatibility. In all other cases we remove the crypto
822 // feature.
823 if (!Args.hasArg(options::OPT_fno_integrated_as)) {
824 Features.push_back("-sha2");
825 Features.push_back("-aes");
826 }
827 }
828 }
829
830 // Propagate frame-chain model selection
831 if (Arg *A = Args.getLastArg(options::OPT_mframe_chain)) {
832 StringRef FrameChainOption = A->getValue();
833 if (FrameChainOption.starts_with("aapcs"))
834 Features.push_back("+aapcs-frame-chain");
835 }
836
837 // CMSE: Check for target 8M (for -mcmse to be applicable) is performed later.
838 if (Args.getLastArg(options::OPT_mcmse))
839 Features.push_back("+8msecext");
840
841 if (Arg *A = Args.getLastArg(options::OPT_mfix_cmse_cve_2021_35465,
842 options::OPT_mno_fix_cmse_cve_2021_35465)) {
843 if (!Args.getLastArg(options::OPT_mcmse))
844 D.Diag(diag::err_opt_not_valid_without_opt)
845 << A->getOption().getName() << "-mcmse";
846
847 if (A->getOption().matches(options::OPT_mfix_cmse_cve_2021_35465))
848 Features.push_back("+fix-cmse-cve-2021-35465");
849 else
850 Features.push_back("-fix-cmse-cve-2021-35465");
851 }
852
853 // This also handles the -m(no-)fix-cortex-a72-1655431 arguments via aliases.
854 if (Arg *A = Args.getLastArg(options::OPT_mfix_cortex_a57_aes_1742098,
855 options::OPT_mno_fix_cortex_a57_aes_1742098)) {
856 if (A->getOption().matches(options::OPT_mfix_cortex_a57_aes_1742098)) {
857 Features.push_back("+fix-cortex-a57-aes-1742098");
858 } else {
859 Features.push_back("-fix-cortex-a57-aes-1742098");
860 }
861 }
862
863 // Look for the last occurrence of -mlong-calls or -mno-long-calls. If
864 // neither options are specified, see if we are compiling for kernel/kext and
865 // decide whether to pass "+long-calls" based on the OS and its version.
866 if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
867 options::OPT_mno_long_calls)) {
868 if (A->getOption().matches(options::OPT_mlong_calls))
869 Features.push_back("+long-calls");
870 } else if (KernelOrKext && (!Triple.isiOS() || Triple.isOSVersionLT(6)) &&
871 !Triple.isWatchOS() && !Triple.isXROS()) {
872 Features.push_back("+long-calls");
873 }
874
875 // Generate execute-only output (no data access to code sections).
876 // This only makes sense for the compiler, not for the assembler.
877 // It's not needed for multilib selection and may hide an unused
878 // argument diagnostic if the code is always run.
879 if (!ForAS && !ForMultilib) {
880 // Supported only on ARMv6T2 and ARMv7 and above.
881 // Cannot be combined with -mno-movt.
882 if (Arg *A = Args.getLastArg(options::OPT_mexecute_only, options::OPT_mno_execute_only)) {
883 if (A->getOption().matches(options::OPT_mexecute_only)) {
884 if (getARMSubArchVersionNumber(Triple) < 7 &&
885 llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6T2 &&
886 llvm::ARM::parseArch(Triple.getArchName()) != llvm::ARM::ArchKind::ARMV6M)
887 D.Diag(diag::err_target_unsupported_execute_only) << Triple.getArchName();
888 else if (llvm::ARM::parseArch(Triple.getArchName()) == llvm::ARM::ArchKind::ARMV6M) {
889 if (Arg *PIArg = Args.getLastArg(options::OPT_fropi, options::OPT_frwpi,
890 options::OPT_fpic, options::OPT_fpie,
891 options::OPT_fPIC, options::OPT_fPIE))
892 D.Diag(diag::err_opt_not_valid_with_opt_on_target)
893 << A->getAsString(Args) << PIArg->getAsString(Args) << Triple.getArchName();
894 } else if (Arg *B = Args.getLastArg(options::OPT_mno_movt))
895 D.Diag(diag::err_opt_not_valid_with_opt)
896 << A->getAsString(Args) << B->getAsString(Args);
897 Features.push_back("+execute-only");
898 }
899 }
900 }
901
902 if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
903 options::OPT_munaligned_access,
904 options::OPT_mstrict_align,
905 options::OPT_mno_strict_align)) {
906 // Kernel code has more strict alignment requirements.
907 if (KernelOrKext ||
908 A->getOption().matches(options::OPT_mno_unaligned_access) ||
909 A->getOption().matches(options::OPT_mstrict_align)) {
910 Features.push_back("+strict-align");
911 } else {
912 // No v6M core supports unaligned memory access (v6M ARM ARM A3.2).
913 if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
914 D.Diag(diag::err_target_unsupported_unaligned) << "v6m";
915 // v8M Baseline follows on from v6M, so doesn't support unaligned memory
916 // access either.
917 else if (Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v8m_baseline)
918 D.Diag(diag::err_target_unsupported_unaligned) << "v8m.base";
919 }
920 } else {
921 // Assume pre-ARMv6 doesn't support unaligned accesses.
922 //
923 // ARMv6 may or may not support unaligned accesses depending on the
924 // SCTLR.U bit, which is architecture-specific. We assume ARMv6
925 // Darwin and NetBSD targets support unaligned accesses, and others don't.
926 //
927 // ARMv7 always has SCTLR.U set to 1, but it has a new SCTLR.A bit which
928 // raises an alignment fault on unaligned accesses. Assume ARMv7+ supports
929 // unaligned accesses, except ARMv6-M, and ARMv8-M without the Main
930 // Extension. This aligns with the default behavior of ARM's downstream
931 // versions of GCC and Clang.
932 //
933 // Users can change the default behavior via -m[no-]unaliged-access.
934 int VersionNum = getARMSubArchVersionNumber(Triple);
935 if (Triple.isOSDarwin() || Triple.isOSNetBSD()) {
936 if (VersionNum < 6 ||
937 Triple.getSubArch() == llvm::Triple::SubArchType::ARMSubArch_v6m)
938 Features.push_back("+strict-align");
939 } else if (Triple.getVendor() == llvm::Triple::Apple &&
940 Triple.isOSBinFormatMachO()) {
941 // Firmwares on Apple platforms are strict-align by default.
942 Features.push_back("+strict-align");
943 } else if (VersionNum < 7 ||
944 Triple.getSubArch() ==
945 llvm::Triple::SubArchType::ARMSubArch_v6m ||
946 Triple.getSubArch() ==
947 llvm::Triple::SubArchType::ARMSubArch_v8m_baseline) {
948 Features.push_back("+strict-align");
949 }
950 }
951
952 // llvm does not support reserving registers in general. There is support
953 // for reserving r9 on ARM though (defined as a platform-specific register
954 // in ARM EABI).
955 if (Args.hasArg(options::OPT_ffixed_r9))
956 Features.push_back("+reserve-r9");
957
958 // The kext linker doesn't know how to deal with movw/movt.
959 if (KernelOrKext || Args.hasArg(options::OPT_mno_movt))
960 Features.push_back("+no-movt");
961
962 if (Args.hasArg(options::OPT_mno_neg_immediates))
963 Features.push_back("+no-neg-immediates");
964
965 // Enable/disable straight line speculation hardening.
966 if (Arg *A = Args.getLastArg(options::OPT_mharden_sls_EQ)) {
967 StringRef Scope = A->getValue();
968 bool EnableRetBr = false;
969 bool EnableBlr = false;
970 bool DisableComdat = false;
971 if (Scope != "none") {
973 Scope.split(Opts, ",");
974 for (auto Opt : Opts) {
975 Opt = Opt.trim();
976 if (Opt == "all") {
977 EnableBlr = true;
978 EnableRetBr = true;
979 continue;
980 }
981 if (Opt == "retbr") {
982 EnableRetBr = true;
983 continue;
984 }
985 if (Opt == "blr") {
986 EnableBlr = true;
987 continue;
988 }
989 if (Opt == "comdat") {
990 DisableComdat = false;
991 continue;
992 }
993 if (Opt == "nocomdat") {
994 DisableComdat = true;
995 continue;
996 }
997 D.Diag(diag::err_drv_unsupported_option_argument)
998 << A->getSpelling() << Scope;
999 break;
1000 }
1001 }
1002
1003 if (EnableRetBr || EnableBlr)
1004 if (!(isARMAProfile(Triple) && getARMSubArchVersionNumber(Triple) >= 7))
1005 D.Diag(diag::err_sls_hardening_arm_not_supported)
1006 << Scope << A->getAsString(Args);
1007
1008 if (EnableRetBr)
1009 Features.push_back("+harden-sls-retbr");
1010 if (EnableBlr)
1011 Features.push_back("+harden-sls-blr");
1012 if (DisableComdat) {
1013 Features.push_back("+harden-sls-nocomdat");
1014 }
1015 }
1016
1017 if (Args.getLastArg(options::OPT_mno_bti_at_return_twice))
1018 Features.push_back("+no-bti-at-return-twice");
1019
1020 checkARMFloatABI(D, Args, HasFPRegs);
1021
1022 return FPUKind;
1023}
1024
1025std::string arm::getARMArch(StringRef Arch, const llvm::Triple &Triple) {
1026 std::string MArch;
1027 if (!Arch.empty())
1028 MArch = std::string(Arch);
1029 else
1030 MArch = std::string(Triple.getArchName());
1031 MArch = StringRef(MArch).split("+").first.lower();
1032
1033 // Handle -march=native.
1034 if (MArch == "native") {
1035 std::string CPU = std::string(llvm::sys::getHostCPUName());
1036 if (CPU != "generic") {
1037 // Translate the native cpu into the architecture suffix for that CPU.
1038 StringRef Suffix = arm::getLLVMArchSuffixForARM(CPU, MArch, Triple);
1039 // If there is no valid architecture suffix for this CPU we don't know how
1040 // to handle it, so return no architecture.
1041 if (Suffix.empty())
1042 MArch = "";
1043 else
1044 MArch = std::string("arm") + Suffix.str();
1045 }
1046 }
1047
1048 return MArch;
1049}
1050
1051/// Get the (LLVM) name of the minimum ARM CPU for the arch we are targeting.
1052StringRef arm::getARMCPUForMArch(StringRef Arch, const llvm::Triple &Triple) {
1053 std::string MArch = getARMArch(Arch, Triple);
1054 // getARMCPUForArch defaults to the triple if MArch is empty, but empty MArch
1055 // here means an -march=native that we can't handle, so instead return no CPU.
1056 if (MArch.empty())
1057 return StringRef();
1058
1059 // We need to return an empty string here on invalid MArch values as the
1060 // various places that call this function can't cope with a null result.
1061 return llvm::ARM::getARMCPUForArch(Triple, MArch);
1062}
1063
1064/// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
1065std::string arm::getARMTargetCPU(StringRef CPU, StringRef Arch,
1066 const llvm::Triple &Triple) {
1067 // FIXME: Warn on inconsistent use of -mcpu and -march.
1068 // If we have -mcpu=, use that.
1069 if (!CPU.empty()) {
1070 std::string MCPU = StringRef(CPU).split("+").first.lower();
1071 // Handle -mcpu=native.
1072 if (MCPU == "native")
1073 return std::string(llvm::sys::getHostCPUName());
1074 else
1075 return MCPU;
1076 }
1077
1078 return std::string(getARMCPUForMArch(Arch, Triple));
1079}
1080
1081/// getLLVMArchSuffixForARM - Get the LLVM ArchKind value to use for a
1082/// particular CPU (or Arch, if CPU is generic). This is needed to
1083/// pass to functions like llvm::ARM::getDefaultFPU which need an
1084/// ArchKind as well as a CPU name.
1085llvm::ARM::ArchKind arm::getLLVMArchKindForARM(StringRef CPU, StringRef Arch,
1086 const llvm::Triple &Triple) {
1087 llvm::ARM::ArchKind ArchKind;
1088 if (CPU == "generic" || CPU.empty()) {
1089 std::string ARMArch = tools::arm::getARMArch(Arch, Triple);
1090 ArchKind = llvm::ARM::parseArch(ARMArch);
1091 if (ArchKind == llvm::ARM::ArchKind::INVALID)
1092 // In case of generic Arch, i.e. "arm",
1093 // extract arch from default cpu of the Triple
1094 ArchKind =
1095 llvm::ARM::parseCPUArch(llvm::ARM::getARMCPUForArch(Triple, ARMArch));
1096 } else {
1097 // FIXME: horrible hack to get around the fact that Cortex-A7 is only an
1098 // armv7k triple if it's actually been specified via "-arch armv7k".
1099 ArchKind = (Arch == "armv7k" || Arch == "thumbv7k")
1100 ? llvm::ARM::ArchKind::ARMV7K
1101 : llvm::ARM::parseCPUArch(CPU);
1102 }
1103 return ArchKind;
1104}
1105
1106/// getLLVMArchSuffixForARM - Get the LLVM arch name to use for a particular
1107/// CPU (or Arch, if CPU is generic).
1108// FIXME: This is redundant with -mcpu, why does LLVM use this.
1109StringRef arm::getLLVMArchSuffixForARM(StringRef CPU, StringRef Arch,
1110 const llvm::Triple &Triple) {
1111 llvm::ARM::ArchKind ArchKind = getLLVMArchKindForARM(CPU, Arch, Triple);
1112 if (ArchKind == llvm::ARM::ArchKind::INVALID)
1113 return "";
1114 return llvm::ARM::getSubArch(ArchKind);
1115}
1116
1117void arm::appendBE8LinkFlag(const ArgList &Args, ArgStringList &CmdArgs,
1118 const llvm::Triple &Triple) {
1119 if (Args.hasArg(options::OPT_r))
1120 return;
1121
1122 // ARMv7 (and later) and ARMv6-M do not support BE-32, so instruct the linker
1123 // to generate BE-8 executables.
1124 if (arm::getARMSubArchVersionNumber(Triple) >= 7 || arm::isARMMProfile(Triple))
1125 CmdArgs.push_back("--be8");
1126}
OffloadArch arch
Definition: Cuda.cpp:77
const Decl * D
static bool DecodeARMFeatures(const Driver &D, StringRef text, StringRef CPU, llvm::ARM::ArchKind ArchKind, std::vector< StringRef > &Features, llvm::ARM::FPUKind &ArgFPUKind)
Definition: ARM.cpp:119
static void checkARMCPUName(const Driver &D, const Arg *A, const ArgList &Args, llvm::StringRef CPUName, llvm::StringRef ArchName, std::vector< StringRef > &Features, const llvm::Triple &Triple, llvm::ARM::FPUKind &ArgFPUKind)
Definition: ARM.cpp:164
static llvm::ARM::FPUKind getARMFPUFeatures(const Driver &D, const Arg *A, const ArgList &Args, StringRef FPU, std::vector< StringRef > &Features)
Definition: ARM.cpp:109
static void checkARMArchName(const Driver &D, const Arg *A, const ArgList &Args, llvm::StringRef ArchName, llvm::StringRef CPUName, std::vector< StringRef > &Features, const llvm::Triple &Triple, llvm::ARM::FPUKind &ArgFPUKind)
Definition: ARM.cpp:146
static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU, std::vector< StringRef > &Features)
Definition: ARM.cpp:133
static void getARMHWDivFeatures(const Driver &D, const Arg *A, const ArgList &Args, StringRef HWDiv, std::vector< StringRef > &Features)
Definition: ARM.cpp:100
static bool hasIntegerMVE(const std::vector< StringRef > &F)
Definition: ARM.cpp:507
static void checkARMFloatABI(const Driver &D, const ArgList &Args, bool HasFPRegs)
Definition: ARM.cpp:183
Scope - A scope is a transient data structure that is used while parsing the program.
Definition: Scope.h:41
Driver - Encapsulate logic for constructing compilation processes from a set of gcc-driver-like comma...
Definition: Driver.h:99
ToolChain - Access to tools for a single platform.
Definition: ToolChain.h:92
const Driver & getDriver() const
Definition: ToolChain.h:252
const llvm::Triple & getEffectiveTriple() const
Get the toolchain's effective clang triple.
Definition: ToolChain.h:282
void getARMArchCPUFromArgs(const llvm::opt::ArgList &Args, llvm::StringRef &Arch, llvm::StringRef &CPU, bool FromAs=false)
FloatABI getDefaultFloatABI(const llvm::Triple &Triple)
Definition: ARM.cpp:387
void setArchNameInTriple(const Driver &D, const llvm::opt::ArgList &Args, types::ID InputType, llvm::Triple &Triple)
void appendBE8LinkFlag(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, const llvm::Triple &Triple)
bool isARMEABIBareMetal(const llvm::Triple &Triple)
Is the triple {arm,armeb,thumb,thumbeb}-none-none-{eabi,eabihf} ?
Definition: ARM.cpp:56
void setFloatABIInTriple(const Driver &D, const llvm::opt::ArgList &Args, llvm::Triple &triple)
bool isARMMProfile(const llvm::Triple &Triple)
Definition: ARM.cpp:30
bool isHardTPSupported(const llvm::Triple &Triple)
Definition: ARM.cpp:208
FloatABI getARMFloatABI(const ToolChain &TC, const llvm::opt::ArgList &Args)
bool isARMAProfile(const llvm::Triple &Triple)
Definition: ARM.cpp:50
bool useAAPCSForMachO(const llvm::Triple &T)
Definition: ARM.cpp:197
std::string getARMTargetCPU(StringRef CPU, llvm::StringRef Arch, const llvm::Triple &Triple)
StringRef getARMCPUForMArch(llvm::StringRef Arch, const llvm::Triple &Triple)
llvm::ARM::ArchKind getLLVMArchKindForARM(StringRef CPU, StringRef Arch, const llvm::Triple &Triple)
getLLVMArchSuffixForARM - Get the LLVM ArchKind value to use for a particular CPU (or Arch,...
Definition: ARM.cpp:1085
int getARMSubArchVersionNumber(const llvm::Triple &Triple)
Definition: ARM.cpp:24
StringRef getLLVMArchSuffixForARM(llvm::StringRef CPU, llvm::StringRef Arch, const llvm::Triple &Triple)
bool isARMBigEndian(const llvm::Triple &Triple, const llvm::opt::ArgList &Args)
llvm::ARM::FPUKind getARMTargetFeatures(const Driver &D, const llvm::Triple &Triple, const llvm::opt::ArgList &Args, std::vector< llvm::StringRef > &Features, bool ForAS, bool ForMultilib=false)
std::string getARMArch(llvm::StringRef Arch, const llvm::Triple &Triple)
ReadTPMode getReadTPMode(const Driver &D, const llvm::opt::ArgList &Args, const llvm::Triple &Triple, bool ForAS)
The JSON file list parser is used to communicate input to InstallAPI.
const FunctionProtoType * T
@ Generic
not a target-specific vector type