clang 20.0.0git
avx10_2_512convertintrin.h
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1/*===--------- avx10_2_512convertintrin.h - AVX10_2_512CONVERT -------------===
2 *
3 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 * See https://llvm.org/LICENSE.txt for license information.
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 *
7 *===-----------------------------------------------------------------------===
8 */
9#ifndef __IMMINTRIN_H
10#error \
11 "Never use <avx10_2_512convertintrin.h> directly; include <immintrin.h> instead."
12#endif // __IMMINTRIN_H
13
14#ifdef __SSE2__
15
16#ifndef __AVX10_2_512CONVERTINTRIN_H
17#define __AVX10_2_512CONVERTINTRIN_H
18
19/* Define the default attributes for the functions in this file. */
20#define __DEFAULT_FN_ATTRS512 \
21 __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-512"), \
22 __min_vector_width__(512)))
23
24static __inline__ __m512h __DEFAULT_FN_ATTRS512 _mm512_cvtx2ps_ph(__m512 __A,
25 __m512 __B) {
26 return (__m512h)__builtin_ia32_vcvt2ps2phx512_mask(
27 (__v16sf)__A, (__v16sf)__B, (__v32hf)_mm512_setzero_ph(), (__mmask32)(-1),
28 _MM_FROUND_CUR_DIRECTION);
29}
30
31static __inline__ __m512h __DEFAULT_FN_ATTRS512
32_mm512_mask_cvtx2ps_ph(__m512h __W, __mmask32 __U, __m512 __A, __m512 __B) {
33 return (__m512h)__builtin_ia32_vcvt2ps2phx512_mask(
34 (__v16sf)__A, (__v16sf)__B, (__v32hf)__W, (__mmask32)__U,
35 _MM_FROUND_CUR_DIRECTION);
36}
37
38static __inline__ __m512h __DEFAULT_FN_ATTRS512
39_mm512_maskz_cvtx2ps_ph(__mmask32 __U, __m512 __A, __m512 __B) {
40 return (__m512h)__builtin_ia32_vcvt2ps2phx512_mask(
41 (__v16sf)__A, (__v16sf)__B, (__v32hf)_mm512_setzero_ph(), (__mmask32)__U,
42 _MM_FROUND_CUR_DIRECTION);
43}
44
45#define _mm512_cvtx_round2ps_ph(A, B, R) \
46 ((__m512h)__builtin_ia32_vcvt2ps2phx512_mask( \
47 (__v16sf)(A), (__v16sf)(B), (__v32hf)_mm512_undefined_ph(), \
48 (__mmask32)(-1), (const int)(R)))
49
50#define _mm512_mask_cvtx_round2ps_ph(W, U, A, B, R) \
51 ((__m512h)__builtin_ia32_vcvt2ps2phx512_mask((__v16sf)(A), (__v16sf)(B), \
52 (__v32hf)(W), (__mmask32)(U), \
53 (const int)(R)))
54
55#define _mm512_maskz_cvtx_round2ps_ph(U, A, B, R) \
56 ((__m512h)__builtin_ia32_vcvt2ps2phx512_mask( \
57 (__v16sf)(A), (__v16sf)(B), (__v32hf)_mm512_setzero_ph(), \
58 (__mmask32)(U), (const int)(R)))
59
60static __inline__ __m256i __DEFAULT_FN_ATTRS512
61_mm512_cvtbiasph_pbf8(__m512i __A, __m512h __B) {
62 return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
63 (__v64qi)__A, (__v32hf)__B, (__v32qi)_mm256_undefined_si256(),
64 (__mmask32)-1);
65}
66
67static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtbiasph_pbf8(
68 __m256i __W, __mmask32 __U, __m512i __A, __m512h __B) {
69 return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
70 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (__mmask32)__U);
71}
72
73static __inline__ __m256i __DEFAULT_FN_ATTRS512
74_mm512_maskz_cvtbiasph_pbf8(__mmask32 __U, __m512i __A, __m512h __B) {
75 return (__m256i)__builtin_ia32_vcvtbiasph2bf8_512_mask(
76 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)_mm256_setzero_si256(),
77 (__mmask32)__U);
78}
79
80static __inline__ __m256i __DEFAULT_FN_ATTRS512
81_mm512_cvtbiassph_pbf8(__m512i __A, __m512h __B) {
82 return (__m256i)__builtin_ia32_vcvtbiasph2bf8s_512_mask(
83 (__v64qi)__A, (__v32hf)__B, (__v32qi)_mm256_undefined_si256(),
84 (__mmask32)-1);
85}
86
87static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtbiassph_pbf8(
88 __m256i __W, __mmask32 __U, __m512i __A, __m512h __B) {
89 return (__m256i)__builtin_ia32_vcvtbiasph2bf8s_512_mask(
90 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (__mmask32)__U);
91}
92
93static __inline__ __m256i __DEFAULT_FN_ATTRS512
94_mm512_maskz_cvtbiassph_pbf8(__mmask32 __U, __m512i __A, __m512h __B) {
95 return (__m256i)__builtin_ia32_vcvtbiasph2bf8s_512_mask(
96 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)_mm256_setzero_si256(),
97 (__mmask32)__U);
98}
99
100static __inline__ __m256i __DEFAULT_FN_ATTRS512
101_mm512_cvtbiasph_phf8(__m512i __A, __m512h __B) {
102 return (__m256i)__builtin_ia32_vcvtbiasph2hf8_512_mask(
103 (__v64qi)__A, (__v32hf)__B, (__v32qi)_mm256_undefined_si256(),
104 (__mmask32)-1);
105}
106
107static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtbiasph_phf8(
108 __m256i __W, __mmask32 __U, __m512i __A, __m512h __B) {
109 return (__m256i)__builtin_ia32_vcvtbiasph2hf8_512_mask(
110 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (__mmask32)__U);
111}
112
113static __inline__ __m256i __DEFAULT_FN_ATTRS512
114_mm512_maskz_cvtbiasph_phf8(__mmask32 __U, __m512i __A, __m512h __B) {
115 return (__m256i)__builtin_ia32_vcvtbiasph2hf8_512_mask(
116 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)_mm256_setzero_si256(),
117 (__mmask32)__U);
118}
119
120static __inline__ __m256i __DEFAULT_FN_ATTRS512
121_mm512_cvtbiassph_phf8(__m512i __A, __m512h __B) {
122 return (__m256i)__builtin_ia32_vcvtbiasph2hf8s_512_mask(
123 (__v64qi)__A, (__v32hf)__B, (__v32qi)_mm256_undefined_si256(),
124 (__mmask32)-1);
125}
126
127static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtbiassph_phf8(
128 __m256i __W, __mmask32 __U, __m512i __A, __m512h __B) {
129 return (__m256i)__builtin_ia32_vcvtbiasph2hf8s_512_mask(
130 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)__W, (__mmask32)__U);
131}
132
133static __inline__ __m256i __DEFAULT_FN_ATTRS512
134_mm512_maskz_cvtbiassph_phf8(__mmask32 __U, __m512i __A, __m512h __B) {
135 return (__m256i)__builtin_ia32_vcvtbiasph2hf8s_512_mask(
136 (__v64qi)__A, (__v32hf)__B, (__v32qi)(__m256i)_mm256_setzero_si256(),
137 (__mmask32)__U);
138}
139
140static __inline__ __m512i __DEFAULT_FN_ATTRS512
141_mm512_cvtne2ph_pbf8(__m512h __A, __m512h __B) {
142 return (__m512i)__builtin_ia32_vcvtne2ph2bf8_512((__v32hf)(__A),
143 (__v32hf)(__B));
144}
145
146static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtne2ph_pbf8(
147 __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
148 return (__m512i)__builtin_ia32_selectb_512(
149 (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_pbf8(__A, __B), (__v64qi)__W);
150}
151
152static __inline__ __m512i __DEFAULT_FN_ATTRS512
153_mm512_maskz_cvtne2ph_pbf8(__mmask64 __U, __m512h __A, __m512h __B) {
154 return (__m512i)__builtin_ia32_selectb_512(
155 (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_pbf8(__A, __B),
156 (__v64qi)(__m512i)_mm512_setzero_si512());
157}
158
159static __inline__ __m512i __DEFAULT_FN_ATTRS512
160_mm512_cvtnes2ph_pbf8(__m512h __A, __m512h __B) {
161 return (__m512i)__builtin_ia32_vcvtne2ph2bf8s_512((__v32hf)(__A),
162 (__v32hf)(__B));
163}
164
165static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtnes2ph_pbf8(
166 __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
167 return (__m512i)__builtin_ia32_selectb_512(
168 (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_pbf8(__A, __B), (__v64qi)__W);
169}
170
171static __inline__ __m512i __DEFAULT_FN_ATTRS512
172_mm512_maskz_cvtnes2ph_pbf8(__mmask64 __U, __m512h __A, __m512h __B) {
173 return (__m512i)__builtin_ia32_selectb_512(
174 (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_pbf8(__A, __B),
175 (__v64qi)(__m512i)_mm512_setzero_si512());
176}
177
178static __inline__ __m512i __DEFAULT_FN_ATTRS512
179_mm512_cvtne2ph_phf8(__m512h __A, __m512h __B) {
180 return (__m512i)__builtin_ia32_vcvtne2ph2hf8_512((__v32hf)(__A),
181 (__v32hf)(__B));
182}
183
184static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtne2ph_phf8(
185 __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
186 return (__m512i)__builtin_ia32_selectb_512(
187 (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_phf8(__A, __B), (__v64qi)__W);
188}
189
190static __inline__ __m512i __DEFAULT_FN_ATTRS512
191_mm512_maskz_cvtne2ph_phf8(__mmask64 __U, __m512h __A, __m512h __B) {
192 return (__m512i)__builtin_ia32_selectb_512(
193 (__mmask64)__U, (__v64qi)_mm512_cvtne2ph_phf8(__A, __B),
194 (__v64qi)(__m512i)_mm512_setzero_si512());
195}
196
197static __inline__ __m512i __DEFAULT_FN_ATTRS512
198_mm512_cvtnes2ph_phf8(__m512h __A, __m512h __B) {
199 return (__m512i)__builtin_ia32_vcvtne2ph2hf8s_512((__v32hf)(__A),
200 (__v32hf)(__B));
201}
202
203static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvtnes2ph_phf8(
204 __m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
205 return (__m512i)__builtin_ia32_selectb_512(
206 (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_phf8(__A, __B), (__v64qi)__W);
207}
208
209static __inline__ __m512i __DEFAULT_FN_ATTRS512
210_mm512_maskz_cvtnes2ph_phf8(__mmask64 __U, __m512h __A, __m512h __B) {
211 return (__m512i)__builtin_ia32_selectb_512(
212 (__mmask64)__U, (__v64qi)_mm512_cvtnes2ph_phf8(__A, __B),
213 (__v64qi)(__m512i)_mm512_setzero_si512());
214}
215
216static __inline__ __m512h __DEFAULT_FN_ATTRS512
217_mm512_cvtnehf8_ph(__m256i __A) {
218 return (__m512h)__builtin_ia32_vcvthf8_2ph512_mask(
219 (__v32qi)__A, (__v32hf)(__m512h)_mm512_undefined_ph(), (__mmask32)-1);
220}
221
222static __inline__ __m512h __DEFAULT_FN_ATTRS512
223_mm512_mask_cvtnehf8_ph(__m512h __W, __mmask32 __U, __m256i __A) {
224 return (__m512h)__builtin_ia32_vcvthf8_2ph512_mask(
225 (__v32qi)__A, (__v32hf)(__m512h)__W, (__mmask32)__U);
226}
227
228static __inline__ __m512h __DEFAULT_FN_ATTRS512
229_mm512_maskz_cvtnehf8_ph(__mmask32 __U, __m256i __A) {
230 return (__m512h)__builtin_ia32_vcvthf8_2ph512_mask(
231 (__v32qi)__A, (__v32hf)(__m512h)_mm512_setzero_ph(), (__mmask32)__U);
232}
233
234static __inline__ __m256i __DEFAULT_FN_ATTRS512
235_mm512_cvtneph_pbf8(__m512h __A) {
236 return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask(
237 (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
238}
239
240static __inline__ __m256i __DEFAULT_FN_ATTRS512
241_mm512_mask_cvtneph_pbf8(__m256i __W, __mmask32 __U, __m512h __A) {
242 return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask(
243 (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
244}
245
246static __inline__ __m256i __DEFAULT_FN_ATTRS512
247_mm512_maskz_cvtneph_pbf8(__mmask32 __U, __m512h __A) {
248 return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask(
249 (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
250}
251
252static __inline__ __m256i __DEFAULT_FN_ATTRS512
253_mm512_cvtnesph_pbf8(__m512h __A) {
254 return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask(
255 (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
256}
257
258static __inline__ __m256i __DEFAULT_FN_ATTRS512
259_mm512_mask_cvtnesph_pbf8(__m256i __W, __mmask32 __U, __m512h __A) {
260 return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask(
261 (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
262}
263
264static __inline__ __m256i __DEFAULT_FN_ATTRS512
265_mm512_maskz_cvtnesph_pbf8(__mmask32 __U, __m512h __A) {
266 return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask(
267 (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
268}
269
270static __inline__ __m256i __DEFAULT_FN_ATTRS512
271_mm512_cvtneph_phf8(__m512h __A) {
272 return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask(
273 (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
274}
275
276static __inline__ __m256i __DEFAULT_FN_ATTRS512
277_mm512_mask_cvtneph_phf8(__m256i __W, __mmask32 __U, __m512h __A) {
278 return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask(
279 (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
280}
281
282static __inline__ __m256i __DEFAULT_FN_ATTRS512
283_mm512_maskz_cvtneph_phf8(__mmask32 __U, __m512h __A) {
284 return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask(
285 (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
286}
287
288static __inline__ __m256i __DEFAULT_FN_ATTRS512
289_mm512_cvtnesph_phf8(__m512h __A) {
290 return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask(
291 (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
292}
293
294static __inline__ __m256i __DEFAULT_FN_ATTRS512
295_mm512_mask_cvtnesph_phf8(__m256i __W, __mmask32 __U, __m512h __A) {
296 return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask(
297 (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
298}
299
300static __inline__ __m256i __DEFAULT_FN_ATTRS512
301_mm512_maskz_cvtnesph_phf8(__mmask32 __U, __m512h __A) {
302 return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask(
303 (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
304}
305
306static __inline __m512h __DEFAULT_FN_ATTRS512 _mm512_cvtpbf8_ph(__m256i __A) {
307 return _mm512_castsi512_ph(_mm512_slli_epi16(_mm512_cvtepi8_epi16(__A), 8));
308}
309
310static __inline __m512h __DEFAULT_FN_ATTRS512
311_mm512_mask_cvtpbf8_ph(__m512h __S, __mmask16 __U, __m256i __A) {
312 return _mm512_castsi512_ph(
313 _mm512_mask_slli_epi16((__m512i)__S, __U, _mm512_cvtepi8_epi16(__A), 8));
314}
315
316static __inline __m512h __DEFAULT_FN_ATTRS512
317_mm512_maskz_cvtpbf8_ph(__mmask16 __U, __m256i __A) {
318 return _mm512_castsi512_ph(
319 _mm512_slli_epi16(_mm512_maskz_cvtepi8_epi16(__U, __A), 8));
320}
321
322#undef __DEFAULT_FN_ATTRS512
323
324#endif // __AVX10_2_512CONVERTINTRIN_H
325#endif // __SSE2__
_mm512_cvtepi8_epi16
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_cvtepi8_epi16(__m256i __A)
Definition: avx512bwintrin.h:1375
_mm512_maskz_cvtepi8_epi16
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_maskz_cvtepi8_epi16(__mmask32 __U, __m256i __A)
Definition: avx512bwintrin.h:1391
__DEFAULT_FN_ATTRS512
#define __DEFAULT_FN_ATTRS512
Definition: avx512bwintrin.h:21
_mm512_slli_epi16
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_slli_epi16(__m512i __A, unsigned int __B)
Definition: avx512bwintrin.h:1498
__mmask64
unsigned long long __mmask64
Definition: avx512bwintrin.h:18
__mmask32
unsigned int __mmask32
Definition: avx512bwintrin.h:17
_mm512_mask_slli_epi16
static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_slli_epi16(__m512i __W, __mmask32 __U, __m512i __A, unsigned int __B)
Definition: avx512bwintrin.h:1504
__mmask16
unsigned short __mmask16
Definition: avx512fintrin.h:42
_MM_FROUND_CUR_DIRECTION
#define _MM_FROUND_CUR_DIRECTION
Definition: avx512fintrin.h:49
_mm512_setzero_si512
static __inline __m512i __DEFAULT_FN_ATTRS512 _mm512_setzero_si512(void)
Definition: avx512fintrin.h:181
_mm256_undefined_si256
static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_undefined_si256(void)
Create a 256-bit integer vector with undefined values.
Definition: avxintrin.h:3675
_mm256_setzero_si256
static __inline __m256i __DEFAULT_FN_ATTRS _mm256_setzero_si256(void)
Constructs a 256-bit integer vector initialized to zero.
Definition: avxintrin.h:4362
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